The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for fabricating a triple well in a semiconductor device.
Generally, semiconductor products are manufactured by a complementary metal-oxide-semiconductor field effect transistor (CMOSFET) technology, that is two kinds of field effect transistor, i.e., NMOSFET and PMOSFET, are configured on one wafer. In order to manufacture the NMOSFET and PMOSFET on one wafer at the same time, a well formation technology is required to divide the NMOSFET and PMOSFET.
A typical well formation technology requires a thermal treatment process of a high temperature for a long time after an ion-implantation process is carried out with a low energy. Since the well formation technology requires a thermal treatment for a long time, there is a disadvantage for an aspect of a semiconductor device fabrication cost and, since a doping concentration of the ion is uniformly decreased in a vertically downward direction from a surface of a wafer. Thus, a control of the semiconductor device is limited.
A profiled well formation technology is recently tried to solve the above problems. In accordance with the profiled well formation technology, a ions are implanted with high-energy to a desired depth, and then a simple thermal treatment process is carried out in order to prevent punchthrough, latch-up and the like.
The well formation technology is classified with a twin-well and a triple well according to the number of kinds of wells formed on one wafer. The triple well is composed of two p-wells and one deep n-well surrounding one of the p-wells. The triple well has advantages that a property of an NMOSFET formed on the p-well can be differently controlled and the NMOSFET has a good property against an external noise. Accordingly, the well formation technology is recently changed from a diffusion twin-well process to the profiled triple well process.
Generally, the NMOSFET formed on the p-well, which is surrounded by the n-well of the triple well, is used as a cell transistor. As a gate length of the cell transistor is decreased, threshold voltage thereof is also decreased, so that a threshold voltage roll-off is caused. Namely, a threshold voltage distribution is broadened with a lack of uniformity. The threshold voltage distribution is broadened, since gate length variation is increased as a size of the transistor becomes smaller and a threshold voltage roll-off of a small transistor is increased. Therefore, in order to secure a uniform characteristic of a cell transistor, it is preferable to have uniform threshold voltage distribution and to solve the threshold voltage roll-off.
FIGS. 1A to 1E are cross sectional views illustrating a fabrication process of a semiconductor device having a triple well according to the prior art.
Referring to FIG. 1A, after a field oxide layer 12 is formed through a shallow trench isolation (STI) on a semiconductor substrate 11, a photosensitive layer is coated and a first mask 13 with the photosensitive layer is formed through a patterning process including exposing and developing processes.
Subsequently, the first mask 13 is used as an ion implantation mask, and n-type impurities are implanted into the semiconductor substrate 11 by using a high energy ion implanter. Thus, a first region 14 of a profiled n-well is formed in the semiconductor substrate 11.
Referring to FIG. 1B, a second mask 15 is formed by patterning a photosensitive layer coated on the semiconductor substrate 11 through exposing and developing processes, the second mask 15 is employed as an ion implantation mask and n-type impurities are implanted into the semiconductor substrate 11 by using a high energy ion implanter, so that second and third regions 16 and 17 of a profiled n-well are formed.
The second region 16 of the profiled n-well is a middle n-well ion implantation region and the third region 17 is a p channel field stop ion implantation region. A numeral reference xe2x80x9818xe2x80x99 in FIG. 1B shows a doping profile of the profiled n-well.
Referring to FIG. 1C, after stripping the first and second masks 13 and 15, a third mask 19 is formed by patterning a photosensitive layer coated on the semiconductor substrate 11 through exposing and developing processes. The third mask 19 is employed as an ion implantation mask and p-type impurities are implanted into the semiconductor substrate 11 by using a high energy ion implanter, so that first and second regions 20, 21 are formed. The first and second regions 20, 21 represent a p-well ion implantation region and an n-channel field stop ion implantation region, respectively. A numeral reference 22 shows a doping profile of the profiled p-well.
Referring to FIG. 1D, the profiled n-well and p-well are activated through a furnace annealing process, so that a triple well formation process is completed. The triple well is composed of a first p-well 23, a deep n-well 24 adjacent to the first p-well 23, a second p-well 25 surrounded by the deep n-well 24 and positioned at a predetermined distance from the first p-well 23.
A transistor to be formed on the second p-well 25 is independent of a transistor to be formed on the first p-well 23. The second p-well 25 has an advantage that can be protected from an external voltage or noise suddenly applied, because the second p-well 25 is surrounded by the deep n-well 24. For this reason, a cell transistor is formed on the second p-well 25.
A photosensitive layer is coated on the semiconductor substrate 11, in which the triple well is completely formed, and a fourth mask 26, exposing a portion of the semiconductor substrate 11 to form a cell transistor, is formed through a patterning process with exposing and developing the photosensitive layer. Thereafter, p-type impurities are implanted into the overall second p-well 25 to adjust a threshold voltage of the cell transistor by using the fourth mask 26 as an ion implantation mask, so that a threshold voltage ion implantation region 27 is formed.
Referring to FIG. 1E, after removing the fourth mask 26, a gate oxide layer 28 and a gate electrode 29A are formed on a predetermined region of the semiconductor substrate 11, and a spacer 29B is formed on sidewalls of the gate electrode 29A. Thereafter, impurities of n and p types are implanted to form an n+ source/drain region 30A of an NMOSFET and a p+ pocket ion implantation region (source/drain region) 30B for a PMOSFET in a peripheral circuit.
FIG. 2 is a detailed cross sectional view along with line xe2x80x98Xxe2x80x99 in FIG. 1E.
Referring to FIG. 2, even though the p-type impurities are implanted to adjust the threshold voltage of the cell transistor according to the prior art as mentioned above, junction loss occurs due to a counter doping effect, since the threshold voltage ion implantation region 27 and the n+ source/drain region of cell junction are mostly overlapped. Thus, resistance and electric field are increased and a refresh time is reduced. Accordingly, reliability of a device is deteriorated.
In order to adjust the threshold voltage necessary to an operation of the cell transistor, pre-determined p-type impurities are required to be implanted in a channel region. If the dose of the p-type impurities is increased, the threshold voltage is increased as much as required. However, the counter doping effect is considerably increased and a refresh characteristic is became worse. Therefore, there is a problem of selecting one appropriate ion implantation condition between to conditions, for forming the source/drain and adjusting the threshold voltage of the cell transistor which have a trade-off relation.
FIG. 3 is a graph showing dopant profiles analyzed with secondary ion mass spectrometer (SIMS) after carrying out a thermal treatment process to the ion implantation region for the threshold voltage and the source/drain region.
Referring to FIG. 3, if an ion-implantation dose of boron is increased in order to adjust the threshold voltage necessary to an operation of the cell transistor, the threshold voltage of the cell transistor may be increased to a desired voltage. However, a counter doping effect is also increased, so that a concentration of a source/drain region that is in a cell junction region is decreased and an electrical loss is largely caused.
Accordingly, a refresh characteristic of a cell junction formed as above is more deteriorated.
It is, therefore, an object of the present invention to provide a method for fabricating a triple well capable of obtaining a threshold voltage of a transistor and suppressing a counter doping effect in a semiconductor device.
In accordance with an aspect of the present invention, there is provided to a method for fabricating a triple well in a semiconductor device, comprising the steps of: forming a first well of a first conductive type with a first concentration lower than a first target concentration, wherein the first concentration is the minimum dose capable of isolating neighboring wells each other; and forming a second well of a second conductive type with a second concentration higher than a second target concentration, wherein the second well includes a first region surrounded by the first well and a second region isolated from the first region by the first well.
In accordance with another aspect of the present invention, there is provided a method forming a semiconductor device, comprising steps of: forming a first well of a first conductive type with a first concentration lower than a first target concentration in a semiconductor substrate, wherein the first concentration is the minimum dose capable of isolating neighboring wells each other; forming a second well of a second conductive type with a second concentration higher than a second target concentration, the second well surrounded by the first well; implanting impurities of the second conductive type to adjust a threshold voltage of a transistor to be formed on a surface of the semiconductor substrate; forming a gate oxide layer and a gate electrode on a predetermined region on the second well; and forming source/drain regions with a first conductive type at both sides of the gate electrode in the second well.